Improved Pipeline data Flow for DySER-based Platform

Zijian Hou1,  Xin Chen2,  Weifeng He1
1Shanghai Jiao Tong University, 2Tongji University


The coarse-grained reconfigurable architecture(CGRA) has advantages over the traditional FPGAs in terms of delay, area and configuration time. DySER is a novel architecture of the CGRA, which can support both functionally specialization and parallelism specialization. In this paper, the relationship between the bandwidth, data transmission time and RC array scale of DySER-based platform have been analyzed. To improve the architecture, we also present a new data transmission mode called incomplete three-phase pipeline. Compared with the original platform, the results show that the improved platform increases the whole time efficiency by 11% to 15%.