In this paper, different characteristics of SRAM cells based on 5 nm underlapped FinFET technology are studied. For the cell structures, which make use of P type access transistors and pre-discharging bitlines to “0” during the read operation, the read current and write margin (WM) are improved. In addition, 8T structures with less underlap for write access transistors are suggested. These structures may have P or N type write access transistor (denoted by 8T-P or 8T-N, respectively) . In these structures, using more underlap for the pull down (pull up) transistors of the structures with the P type (N type) access transistors and doubling the fins of the write access transistor in the 8T structure may improve the WM significantly without any adverse effect on the read SNM. The results of HSPICE simulations show about 50% improvement for the write margin. Also, the effects of the process variation on various characteristics are investigated. It is revealed that the proposed 8T-P has a WM cell sigma higher than six for supply voltages as low as 0.25 V.