Design of a Low-power UHF RFID Tag Baseband with Three-level Clock-gating Technique

Haibo Liao1,  Bin Wang1,  Weixin Kong2,  Yonghua Hu2,  Hui Du2
1Hangzhou Dianzi University, 2Rice Microelectronics Co. Ltd.


We presented in this paper a low-power baseband processor with a novel clock-gating design technique for passive UHF RFID Tag that demands low power consumption design and commercially competitive area saving. To minimize the power consumption,the baseband processor adopts the asynchronous design and uses the novel three-level clock-gating control for the first time,from top design to bottom cell at the best efforts to eliminate the cells redundant activities. The baseband supports eleven mandatory commands and one optional command and in full compliance with the EPCTM Class-1 Generation-2 V1.2.0 protocol. The system clock frequency of the tag chip with 512b EEPROM is 1.92MHZ. The Tag is fabricated in SMIC 0.18μm EEPROM process. Test results indicate that the processor consume 2.91μW at 1V supply voltage and occupies an area of 0.088mm2.