Power Efficient Router Architecture for Wireless Network-on-Chip

Hemanta Kumar Mondal1, Sri Harsha Gade2, Raghav Kishore1, Shashwat Kaushik1, Sujay Deb1
1IIIT Delhi, 2iiitd.ac.in


Wireless Networks-on-Chip (WNoCs) offer the most promising solution to overcome limitations of conventional Networks-on-Chip (NoCs) for long distance communications in future many-core processors. Detailed investigations of NoC with wireless interfaces (WIs) highlight their many benefits. But, static power consumption associated with WI components and routers, in general, is considerably high. By selectively turning off unused/ rarely used routers, static power consumption can be reduced. Additionally, in WNoCs with broadcast-capable antennas, only a single active wireless communication is allowed and many WIs remain inactive for longer duration and dissipate static power. To avoid this, we propose power-efficient fine-grained router architecture (FGRA) to keep power consumption to minimum. We also minimize wake-up latency by using an approach to wake-up a power-gated transceiver whenever signal is detected at its receiving antenna. We also propose non-blocking bypass channel (NBBC) to bypass power-gated routers and minimize routing latency and contention. We evaluate our proposed router design in presence of real and synthetic traffic patterns. FGRA saves up to 88.76% (per base router) and 62.50% (per WI) of static power as compared to regular architecture with 2.42% area overhead. Based on the utilization, FGRA also reduces overall network power consumption by 37.20% on average with negligible performance degradation. Design considerations for augmenting existing NoCs with these power-gated routers and corresponding overheads are also presented.