This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSV’s EM objective function is used, which replaces the current employed time-consuming finite-element-method (FEM) based simulation. Considering TSV’s EM is mutually influenced by neighboring TSVs (due to TSV EM’s dependence on TSV-induced thermal mechanical stress) and strongly temperature-dependent, iterative optimizations are performed to obtain the optimal TSV’s distribution and a desired TSV’s temperature. Finally using a compact thermal model and simulated annealing, all logic gates are placed such that the desired temperature profile is reached. Results show that compared with conventional wirelength centered 3D placer such as 3Dcraft, our design achieves 3.41x longer mean-time-to-failure (MTTF), with only 3% wirelength overhead.