Performance Modeling and Optimization for On-Chip Interconnects in 3D Memory Arrays

Javaneh Mohseni, Chenyun Pan, Azad Naeemi
Georgia Institute of Technology


This paper presents the major limitations to the interconnect technology scaling in 2D and 3D memory systems at future technology nodes from 9.5nm to 3nm. Impacts of both evolutionary and radical potential solutions to the BEOL scaling problem are quantified. First, by developing models for the access time, dynamic power and energy consumption of a memory system, the impact of interconnects on 3D memory performance is investigated. To address the performance bottlenecks of memory systems, different 3D memory configurations are investigated and optimized. To address the interconnect challenge, novel interconnect technologies are considered which include using single crystal copper interconnects, and changing the diffusion barrier material and thickness. In addition, structural changes in 3D memory systems are introduced to minimize the limits imposed by interconnects. The solutions to memory array scaling enabled by 3D integration are investigated. The impact of through-silicon via (TSV) and monolithic inter-tier via (MIV) technologies on the performance of 3D memory arrays are studied. Finally by studying 3D memory system performance for technology nodes up to the year 2026, the performance bottlenecks of a memory array and the solutions provided by 3D integration are identified.