5nm: Has the Time for a Device Change Come?

Praveen Raghavan, Marie Garcia Bardon, Pieter Schuddinck, Doyoung Jang, Dmitry Yakimets, Rogier Baert, Peter Debacker, Diederik Verkest, Aaron Thean


As we scale further towards 7nm/5nm, where power becomes a primary metric for scaling the need to maintain leakage under control while having performance gains is paramount. This paper debates the advantages and disadvantages of possible transition from FinFET to nanowire for 5nm as the trade-off between sub-threshold slope and device Idsat has to be made and between performance and energy consumption. We discuss in detail the need for transition from FinFET to nano-wire both from a device and an SoC point of view.