Transistor Design for 5nm and Beyond: Slowing Down Electrons to Speed Up Transistors

Victor Moroz1, Joanne Huang1, Reza Arghavani2
1Synopsys, 2Lam Research


Analysis of the key band structure properties for MOSFET channel material are investigated in a wide range for nanowires with design rules scaling from 5 nm down to 2 nm. Three-dimensional Non-Equilibrium Green’s Functions (NEGF) method is employed to calculate the on-state currents for different channel band structures and a fixed off-state current. Results of the analysis show that the optimal effective mass increases with transistor scaling from 0.1 at 5 nm design rules up to 0.4 at 2 nm design rules. There is a gentle performance degradation for effective masses that are heavier than optimal, and there is a steep performance penalty for the lighter electrons due to the direct source-to-drain tunneling through the barrier. Different Si crystal orientations can be chosen to get close to theoretically possible optimal performance, and stress can be used to slow down the electrons. Silicon scales well down to at least 2 nm technology node, and properties of typical 2D materials like MoS2 are close to optimal. However, high-mobility materials like Ge or III-V are far outside of the optimal property range and do not scale well. One other key aspect of transistor scaling potential is its inherent random variability. Analysis of transistor performance sensitivity to geometry fluctuations shows that 5 nm nanowires are less sensitive than FinFETs to the channel length variation, but sharply more sensitive than FinFETs to fin width variation. Specific FinFET and nanowire sensitivity to geometry fluctuations can be used to determine the spec for future equipment that is necessary for high yield nanowire manufacturing.