IoT Memory Trends

Rashmi Sachan
Texas Instruments


The INTERNET OF THINGS (IOT) is the phenomena of smart connected objects throughout the world. Recent reports shows connected objects to reach 50 billion by 2020. Many of these small devices will be powered by embedded microprocessors. The newer IOT microprocessors need to integrate memory into itself to address energy and bandwidth limitation of traditional separate memory and compute. This new microprocessor architecture will drive the new memory architecture and technology. For example Non Volatile Information Processing ( NVIP) which reduce power can be implemented by integrating Non Volatile memory (NVM) into logic circuits. The manufacturing cost at sub 20nm memories has increased multiple folds due to added complexity. Extreme Ultraviolet (EUV) lithography tools have the challenge of control of defects in processed masks etc. New memory technology will involve more than moving electrons but moving atoms or spins.(ReRAM, FeRAM, MRAM etc). The scaling limit of electron based devices will be limited due to quantum-mechanical tunneling. Smaller devices need to be atoms whose mass is greater than of an electron. The new ReRAM reportedly has operating voltage 5-10X lower than NV Memory. FeRAM has very good writing energy along with non-volatility feature but struggle with scaling below 130nm. Power consumption is the biggest challenge for IOT devices eg. Sensors, Tags and Healthcare monitors to be able to sustain longer battery lifespan. Multiple energy harvesting techniques are being invented which convert energy from physical energy sources eg. temperature and pressure difference. Lowering the voltage reduces the power consumption by two times Power is proportional to V^2. Reducing the threshold voltage (VT) of CMOS devices bring down the maximum voltage requirement but it also increases the leakage in OFF state. As device length reduces in order to reduce device area, leakage increases many folds. Gate leakage and subthreshold leakage are significant leakage contributors in L<65nm technologies. GIDL (gate induced drain leakage) and BTBT ( band to band tunneling) dominates on junction leakage. Memory power is a significant contributor for a Microprocessor Chip and reducing it is a challenge. The main contribution of memory power is bit-line capacitance and its switching power. The SRAM memory voltage does not scale linearly with technology as lowered voltage impacts the memory bit-ell stability and robustness ( Signal to Noise Margin ). Several Assist scheme are being deployed in memories to improve write ability and read stability during operation. To reduce bit-line capacitance, hierarchal bit-lines and blocking techniques are used at the cost of added area and metal resources. Few techniques to reduce memory leakage are using multi-Vth design where non timing critical devices are in Higher Vth than timing critical transistors to reduce overall leakage, use of higher thickness oxide to increase Vth, higher channel length, multiple body bias, dynamic Vth scaling etc. Power management circuits control memory to remain in standby or retention mode when not accessed; this reduces the memory leakage significantly. Dynamic retention till access (RTA) use automatic control of memory blocks to be in retention mode based on address information. With dynamic process, voltage and temperature control, SOCs can adjust itself for optimum performance and power. These smart ultra-low-power memories will power the next generation SOCs for IOT applications.