Architecting STT Last-Level-Cache for Performance and Energy Improvement

Fazal Hameed1 and Mehdi Tahoori2
1Chair of Dependable Nano Computing KIT - Karlsruhe Institute of Technology, 2Karlsruhe Institute of Technology


Spin Transfer Torque Random Access Memory (STT-RAM) is a promising alternative to DRAM memory for Last-Level-Cache due to low leakage power and the absence of refresh energy. Recent research has illustrated the performance and energy benefits of STT-RAM over DRAM memory via reducing the number of row buffer conflicts. However, state-of-the-art techniques do not fully exploit the cache access patterns which can lead to a reduced performance and energy efficiency. We therefore propose two row buffer bypass policies and an alternative row buffer organization to reduce the number of row buffer conflicts in STT-RAM based Last-Level-Cache architectures. We evaluate our policies and organization for different combinations of SPEC2006 benchmarks and compare their performance and energy with recent proposal for STT-RAM based memory. Our proposal reduces the average energy consumption compared to the state-ofthe-art.