Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes

Deepak Kumar Arora1, Darayus Adil Patel2, Shahabuddin Qureshi1, Sanjay Kumar1, Navin Kumar Dayani1, Balwant Singh1, Sylvie Naudet1, Arnaud Virazel3, Alberto Bosio3
1STMicroelectronics, 2STMicroelectronics / LIRMM, 3LIRMM


This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.