Optimizing SRAM Bitcell Reliability and Energy for IoT Applications

Harsh Patel, Farah Yahya, Benton Calhoun
University of Virginia


This paper compares six different 8T SRAM bitcells targeting different design space requirements - such as reliability and low power/energy - for Internet of Things (IoT) applications. Different bitcells leverage the varying characteristics of highthreshold (high-VT) and standard-threshold (standard-VT) devices to affect SRAM metrics like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and variability. The reliability for each bitcell over process (intra- and inter-die variation) and temperature variation is also evaluated. Measured results for a commercial 130nm test chip compare the most promising two 8T bitcell structures targeting low leakage and low energy.