Memory circuits have become dominant components in IC designs especially in mobile and IoT era, which demands extremely high integration density as well as high reliability under process and environment variations. As density grows, the same number of fail bits becomes extremely rare events, hence one of the most challenging design aspects is to accurately predict the extremely low failure rate. In order to overcome the intractability of conventional Monte Carlo methods, many importance sampling methods have been suggested. In this paper, a novel multiple shift-vector importance sampling method using support vector machine and clustering (MSVISC) is proposed and its contributions to high density memory design in aspects of both fabrication process and circuit design are demonstrated. To the best of the authors’ knowledge, this is the first report of advanced importance sampling method applied to the state-of the-art DRAM designs.