A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications

Abhishek Roy1, Peter Grossmann2, Steven Vitale2, Benton Calhoun3
1University of Virginia, 2MIT Lincoln Laboratory, Lexington, MA USA, 3University of Virginia, Charlottesville, VA USA


This paper presents an implementation of a 16-bit MSP430 processor for ultra-low-power (ULP) systems catering to battery-less wireless sensor nodes, biomedical, and other IoT applications. Implemented in a custom extremely low power (xLP) 90nm FDSOI process, the processor consumes 1.3μW operating at 0.4V while executing a peak detection algorithm at 250 kHz. It supports the standard MSP430 instruction set architecture (ISA) and demonstrates QRS peak detection for an Electrocardiogram (ECG) application. The measured energy while executing peak detection at 250 kHz was 5pJ per cycle at 0.4V. The fabricated xLP devices show 55% reduction in threshold voltage (Vth) variation compared to similar-sized transistors in a traditional FDSOI process.