Monolithic 3D IC Design: Power, Performance, and Area Impact at 7nm

Kartik Acharya1, Kyungwook Chang1, Bon Woong Ku1, Shreepad Panth1, Saurabh Sinha2, Brian Cline2, Greg Yeric2, Sung Kyu Lim3
1Georgia Institute of Technology, 2ARM Inc, 3Georgia Tech


In this paper, we present a comprehensive study of full-chip power, performance, and area metric for monolithic 3D (M3D) IC designs at the 7nm technology node. We investigate the benefits of M3D designs using our predictive 7nm FinFET libraries. This paper outlines detailed iso-performance power comparisons between M3D and 2D full-chip GDSII designs using both 7nm high performance (HP) and low stand-by power (LSTP) library cells. We achieve significant wire-length and buffer reduction with 7nm HP M3D designs over 2D counterparts, thus more power saving at high iso-performance frequency. In addition, this power saving is also realized in 7nm LSTP M3D designs running at low iso-performance frequencies. We also study the impact of clock tree design on the clock power consumption in M3D designs. Lastly, we demonstrate the impact of clock tree partitioning on the total power of full-chip M3D designs. Our experiments show that 7nm HP and LSTP M3D designs outperform its 2D counterparts by 11% and 10% on average, respectively.