Design Guidelines for Embedded NoCs on FPGAs

Noha Gamal1, Hossam Fahmy2, Yehea Ismail3, Hassan Mostafa2
1Mentor Graphics, 2Cairo University, 3CND at Zewail city and AUC


Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-topoint interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration (PDR), and reduce compile time and improve system performance. We compared FPGA-specific NoC components on soft and hard implementations and analyzed the efficiency gab between the two technologies to get design constraints in this space. Input module that includes memory buffers, implemented using block RAMs (BRAMs), has less 1.8x area, 2.9x delay and 5.3x power. Switch has the largest gab: 90x area, 7x delay and 53x power. If the router is totally hard implemented, this will save 9x area, 3.7x delay and 12x power. By comparing our results with same flow on ASIC-specific router, we show that using FPGA-specific NoCs design improves utility with 3x in area with slight increase in delay.