Performance Evaluation of Stacked Gate-All-Around MOSFETs at 7 and 10 nm Technology Nodes

Meng-Yen Wu and Meng-Hsueh Chiang
National Cheng Kung University


Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.