0.5-V 50-mV-Swing 1.2-GHz 28-nm-FD-SOI 32-bit Dynamic Bus Architecture with Dummy Bus

Khaja Ahmad Shaik, Kiyoo Itoh, Amara Amara
Institut supérieur d'électronique de Paris (ISEP)


To achieve a 0.5-V low-power high-speed robust bus, a dynamic bus architecture, combined with a dynamic driver and a dynamic receiver for small leakage current with stacked MOSFETs, is proposed. In particular, the dynamic driver enables high speed even at 0.5 V with increased gate-over-drive by changing the power lines from VDD/2 in the standby mode to VDD in the active mode. It further speeds up with the help of another proposal of a dummy bus for tracking the bus-voltage detecting point for reducing the bus swing. Robustness of each proposal is investigated by Monte Carlo simulation. Then, a 0.5-V 28-nm-FD-SOI 32-bit bus architecture using the proposals is evaluated by simulation. The power-supply bounce noise and the reduction are also investigated here through the layout. As a result, it turns out that the architecture has a potential of operating a 1-pF bus at a 50-mV swing, 1.2 GHz, and a standby current of 1.1 µA, with x3-5 faster and more than two-order lower standby current than the conventional static architecture.