Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array

Hari Shanker Gupta1, Satyajit Mohapatra2, Nihar R. Mohapatra2, D K Sharma3
1Space Applications Centre, 2Department of Electrical Engineering, Indian Institute of Technology, Gandhinagar, Ahmedabad, India, 3Department of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India


High performance pixel design for 550Kē full well capacity, 10μm pixel pitch and 65dB dynamic range is challenging on typical CMOS process. In general silicon processes are un-optimized for critical optical parameters. Therefore, the spectral response and photo-sensitive simulation are the immediate requirements. This paper highlights a methodology for high performance imaging pixel design in a typical CMOS process and optimizing its quantum efficiency over a wide spectral range of 0.1μ to 0.9μm wavelength. It also introduces an design approach for such systems with the help of TCAD tool for photo sensitivity simulation and HSPICE simulator for integrated performance verification. The quantum efficiency of pixels has been optimized through layout design technique and verified through TCAD simulation. The integrated simulation and post layout results shows good agreement with post-layout simulation of a test chip design of 4×4 pixel area array for 50% quantum efficiency and dynamic range of more than 65dB using 180 nm CMOS process.