Low-Leakage and Process-Variation-Tolerant Write-Read Disturb-Free 9T SRAM Cell Using CMOS and FinFETs

Ayushparth Sharma and Kusum Lata
The LNM Institute of Information Technology


For 22nm SoC products, we propose a 9T SRAM cell with low voltage operation and low leakage power using Bulk CMOS and FinFETs. This is achieved by adopting single-ended write & read operation and serial transistor assembly for stacking effect. Proposed cell is designed and simulated in CMOS 22nm technology and results shows that proposed 9T cell achieves 42.2% improvement in write noise margin, 30.1% and 24.7% reduction in read & write power respectively,10^7 times reduced read and write failure probabilities, 31.8% reduced leakage current when compared to Conventional 6T SRAM cell design. Also, designing SRAM cells using fin-shaped field effect transistors shows more process variation tolerance and improvement of ~23% in power consumption, 2.04 times read SNM at VDD=500mV over CMOS design counterpart. Leakage reduction and enhanced read-write stability of proposed cell are verified under process variations. Also, proposed cell is observed to have 32% larger layout area when compared to Conv. 6T design.