Ultra-Low-Power Compact TFET Flip-Flop Design for High-Performance Low-Voltage Applications

Navneet Gupta1, Adam Makosiej2, Andrei Vladimirescu3, Amara Amara3, Costin Anghel3
1Institut supérieur d'électronique de Paris, France; LETI, Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA-LETI) France;, 2CEA-LETI, France, 3Institut supérieur d'électronique de Paris, France


In this paper, we propose a novel TFET Flip-Flop (TFET-FF) designed to address the requirements of ULP (Ultra-Low-Power) applications, like IoT (Internet of Things), while maintaining high performance. The performance of the proposed design in terms of power, area and speed is compared with different flip-flop designs present in literature for MOSFETs, TFETs and FinFETs. The proposed flip-flop supports voltage scaling and works for supply voltages from 0.3V to 0.6V. Leakage is improved by 4 to 7 decades in comparison to state-of-the-art TFET, FinFET and MOSFET designs. With neither feedback for latch implementation nor device stacking, the TFET-FF speed is comparable or exceeds the speed of High-Performance FinFET implementation for VDD = 0.3V/0.5V. The number of transistors used for the proposed TFET-FF is reduced by 50% in comparison to CMOS and FinFET implementations.