Device/System Performance Modeling of Stacked Lateral NWFET Logic

Victor Huang1, Chenyun Pan1, Azad Naeemi1, Dmitry Yakimets2, Praveen Raghavan2
1Georgia Institute of Technology, 2imec


A new device structure using two layers of lateral nanowire transistors (LFET) stacked on top of each other is proposed for an inverter and 2-input NAND (NAND2) gate. By stacking PFETs on top of NFETs, the effective cell footprint areas of an inverter and a NAND2 are reduced by 50% and 33%, respectively. Based on the capacitance simulations, the stacked structure provides a 13% reduction in input gate capacitance for a minimum sized inverter thanks to a shorter NFET cell. The system-level simulation results show up to 12.9% of the power saving at the supply voltage of 0.6V.