Rev. 2, 2/11/2018
Chair: Vinod Viswanath, Real Intent
Co-Chair: Sreejit Chakravarty, Intel
112 |
10:20AM 1A.2 A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators Aydin Dirican, Cagatay Ozmen, Martin Margala University of Massachusetts Lowell |
14 |
11:00AM 1A.4 Augmenting ESD and EOS Physical Analysis with Per Pin ESD and Leakage DFT Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono Intel Corporation |
Chair: Rajesh Berigei, Consultant
Co-Chair: Jingtong Hu, University of Pittsburgh
75 |
10:40AM 1B.3 Optimizing Energy in a DRAM based Hybrid Cache Jiacong He1 and Joseph Callenes-Sloan2 1University of Texas at Dallas, 2California Polytechnic State University |
Chair: Shih-Hung Chen, IMEC
Co-Chair: Jayita Das, Intel Corporation
48 |
10:20AM 1C.2 LUPIS : Latch-Up Based Ultra Efficient Processing-in-Memory System Joonseop Sim1, Mohsen Imani1, Woojin Choi1, Yeseong Kim2, Tajana Rosing1 1UCSD, 2University of California San Diego |
92 |
10:40AM 1C.3 Energy efficient neuromorphic processing using spintronic memristive device with dedicated synaptic and neuron terminology Zoha Pajouhi Intel Corporation |
Chair: Srini Krishnamoorthy, AMD
Co-Chair: Srinivas Katkoori, University of South Florida
90 |
3:45PM 2A.1 Recognition of Regular Layout Structures Yu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin Yuan Ze University |
19 |
4:05PM 2A.2 A Simplified Methodology for Complex Analog Module Layout Generation Pradeep Chawda Texas Instruments |
83 |
4:25PM 2A.3 Process Variation Aware D-Flip-Flop Design using Regression Analysis Shinichi Nishizawa1 and Hidetoshi Onodera2 1Saitama University, 2Kyoto University |
51 |
4:45PM 2A.4 Clock Buffer and Flip-flop Co-optimization for Reducing Peak Current Noise Joohan Kim1 and Taewhan Kim2 1Samsung Electronics, 2Seoul National University |
101 |
5:05PM 2A.5 Parasitic-Aware gm/ID-Based Many-Objective Analog/RF Circuit Sizing Tuotian Liao1 and Lihong Zhang2 1Memorial University of Newfoundland, 2Memorial University of Newfoundlan |
Chair: Rajesh Berigei, Consultant
Co-Chair: Jingtong Hu, University of Pittsburgh
46 |
3:45PM 2B.1 A Loop Structure Optimization targeting High-level Synthesis of Fast Number Theoretic Transform Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa Waseda University |
Chair: Swaroop Ghosh, Pennsylvania State University
66 |
5:55PM P1 Network on Interconnect Fabric Boris Vaisband, Adeel Bajwa, Subramanian Iyer University of California, Los Angeles |
38 |
5:55PM P3 Body-Biasing Assisted Vmin Optimization for 5nm-Node Multi-Vt FD-SOI 6T-SRAM Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang National Cheng Kung University |
30 |
5:55PM P4 Measuring the effectiveness of ISO26262 compliant Self Test Library Frederico Pratas, Thomas Dedes, Andrew Webber, Majid Bemanian, Itai Yarom MIPS |
26 |
5:55PM P5 An Online Framework for Diagnosis of Multiple Defects in Scan Chains Sarmad Tanwir1, Michael Hsiao1, Loganathan Lingappan2 1Virginia Tech, 2Intel Corporation |
6 |
5:55PM P6 Routing at Compile Time Chun-Xun Lin, Tsung-Wei Huang, Martin Wong University of Illinois at Urbana-Champaign |
84 |
5:55PM P7 Uncertainty Aware Mapping of Embedded Systems for Reliability, Performance, and Energy Wenkai Guan, Milad Ghorbani Moghaddam, Cristinel Ababei Marquette University |
5 |
5:55PM P8 On the Write Energy of Non-Volatile Resistive Crossbar Arrays With Selectors Albert Ciprut and Eby G. Friedman University of Rochester |
97 |
5:55PM P10 Generic System-Level Modeling and Optimization for Beyond CMOS Device Applications Victor Huang, Chenyun Pan, Azad Naeemi Georgia Institute of Technology |
69 |
5:55PM P12 Reliable Memory PUF Design for Low-Power Applications Mohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Tahoori Karlsruhe Institute of Technology |
25 |
5:55PM P13 An ESD Transient Clamp with 494 pA Leakage Current in GP 65 nm CMOS Technology Mahdi Elghazali, Manoj Sachdev, Ajoy Opal University of Waterloo |
80 |
5:55PM P15 An Automated Flow for Design Validation of Switched Mode Power Supply Pradeep Chawda1 and Srikrishna Srinivasan2 1Texas Instruments, 2Texas Instruments Inc |
Chair: Vinod Viswanath, Real Intent
Co-Chair: Sreejit Chakravarty, Intel
50 |
10:00AM 3A.1.1 A Technique to Aggregate Classes of Analog Fault Diagnostic Data Based on Association Rule Mining Ruslan Dautov1 and Sergey Mosin2 1Shenzhen University, 2Kazan Federal University |
59 |
10:20AM 3A.1.2 Extracting Hardware Assertions Including Word-Level Relations over Multiple Clock Cycles Mami Miyamoto and Kiyoharu Hamaguchi Shimane University |
Chair: Srini Krishnamoorthy, AMD
Co-Chair: Srinivas Katkoori, University of South Florida
18 |
11:00AM 3A.2.2 Verification Methodology to Guarantee Low Routing Resistance to Well Taps MOHAMMED FAKHRUDDIN, Kuok-Khian Lo, James Karp, Michael Hart, Min-Hsing Chen Xilinx, Inc. |
Chair: Kurt Schwartz, Texas Instruments, Inc
Co-Chair: Jose Pineda de Gyvez, Eindhoven Univ of Technology
10 |
10:00AM 3B.1 Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems Przemyslaw Mroszczyk and Vasilis Pavlidis The University of Manchester |
98 |
10:20AM 3B.2 Back-Bias Generator for Post-Fabrication Threshold Voltage Tuning Applications in 22nm FD-SOI Process Arif Siddiqi, Navneet Jain, Mahbub Rashed Global Foundries |
Chair: Pradeep Chawda, Texas Instruments, Inc
Co-Chair: Ali A. Shahi, Globalfoundaries
124 |
10:00AM 3C.1 IoT Gateways - Living on the Edge Alfred Gomes Axiomware |
125 |
10:20AM 3C.2 New AC Resistance Calculation of Printed Spiral Coils for Wireless Power Transfer Gaorong Qian, Yuhua Cheng, Guoxiong Chen, Gaofeng Wang Hangzhou Dianzi University |
28 |
10:40AM 3C.3 An Automated Design Flow for Synthesis of Optimal Multi-layer Multi-shape PCB Coils for Inductive Sensing Applications Pradeep Chawda Texas Instruments |
57 |
11:00AM 3C.4 When "things" get older - Exploring Circuit Aging in IoT Applications Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea Stan University of Virginia |
Chair: Aswin Mehta, Texas Instruments, Inc
Co-Chair: Rajan Beera, Pall Corporation
117 |
11:40AM 4A.1.1 A systematic study of hotspot detection in physical designs using machine learning Piyush Verma1, Robert Pack2, Sriram Madhavan2 1Globalfoundries Inc., 2Globalfoundaries |
Chair: Yang (Cindy) Yi, Virginia Tech
Co-Chair: Aswin Mehta, Texas Instruments, Inc.
71 |
12:00PM 4A.2.1 A Deep Learning Based Approach for Analog Hardware Implementation of Delayed Feedback Reservoir Computing System Jialing Li, Kangjun Bai, Lingjia Liu, Yang Yi Virginia Tech |
Chair: Jose Pineda de Gyvez, Eindhoven Univ of Technology
Co-Chair: Raviprakash Rao, Texas Instruments, Inc
74 |
12:00PM 4B.2 Parallel implementation of finite state machines for reducing the latency of stochastic computing Cong Ma and David Lilja University of Minnesota |
56 |
12:40PM 4B.4 A Low-Power Configurable Adder for Approximate Applications Tongxin Yang, Tomoaki Ukezono, Toshinori Sato Fukuoka University |
Chair: Pradeep Chawda, Texas Instruments, Inc
Co-Chair: Ali A. Shahi, Globalfoundaries
120 |
12:20PM 4C.3 Power Management Factors and Techniques for IoT Design Devices Anupriya Prasad and Pradeep Chawda Texas instruments |
Chair: Yang (Cindy) Yi, Virginia Tech
Co-Chair: Aswin Mehta, Texas Instruments, Inc.
78 |
3:40PM 5A.1 Quantized Neural Networks with New Stochastic Multipliers Bingzhe Li1, MohammadHassan Najafi1, Bo Yuan2, David Lilja1 1University of Minnesota-twin cities, 2City University of New York |
13 |
4:20PM 5A.3 Deep Neural Network Acceleration Framework Under Hardware Uncertainty Mohsen Imani1, Pushen Wang1, Tajana Rosing2 1University of California San Diego, 2UCSD |
Chair: Jon Nafziger, Texas Instruments, Inc
Co-Chair: Swaroop Ghosh, Pennsylvania State University
116 |
4:00PM 5B.2 High-Level Synthesis of Key Based Obfuscated RTL Datapaths Sheikh Ariful Islam and Srinivas Katkoori University of South Florida |
Chair: Jayita Das, Intel Corporation
122 |
4:05PM 5C.2 Low cost & power CNN/Deep learning solution for Automated Driving Mihir Mody, Kumar Desappan, Pramod Swami, Manu Mathew, Soyeb Nagori Texas Instruments, Inc |