Reverse Engineering Word-Level Models from Look-Up Table Netlists

Ram Venkat Narayanan, Aparajithan Nathamuni-Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
University of Cincinnati


Reverse engineering of FPGA designs from bitstreams to RTL models aid in understanding the high-level function of the design and for validating and reconstructing legacy designs. Fast carry-chains are commonly used in the synthesis of operators in FPGA designs. We propose a method to detect word-level structures by analyzing these carry-chains in LUT (Look-Up Table) level netlists. We also present methods to adapt existing techniques to identify combinational operations and sequential modules in ASIC netlists to LUT netlists. All developed and adapted techniques are consolidated into an integrated tool-chain to aid in reverse engineering of word-level designs from LUT-level netlists. When evaluated on a set of real-world designs, the tool-chain infers 34% to 100% of the gates in the netlist to be part of a known word-level operation or a known sequential module.