Modern SoCs are designed by integrating several IPs using various interconnect layers(NoC). Although the exact functionality of the device is of the highest importance, the correct behavior in terms of performance is a crucial factor. To gain a competitive edge in the market, safety-critical devices (such as automotive devices) must meet various performance-related requirements. In this paper, we propose a methodology that includes the automatic addition of expected performance numbers of each performance test in the testbench. The definition of two proposed performance metrics, developing a proposed performance scoreboard to implement a self-check mechanism in UVM testbench, and regression management of several hundred performance verification test cases run on SoC RTL. The proposed methodology has been applied to multiple commercial SoCs, both at the chip and sub-system levels, and has detected several performance design flaws during the initial design phase. It has been improved the productivity of the design team also. In complicated SoCs, it has been proven useful without any established standard technique for performance verification at the SoC level.