Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect Memories

Arun Govindankutty1, Shamiul Alam2, Sanjay Das1, Ahmedullah Aziz2, Sumitha George1
1North Dakota State University, 2The University of Tennessee, Knoxville


Cryogenic memory technologies are garnering attention due to their natural synergy with quantum-computing systems, space applications, and ultra-fast superconducting processors. A recently proposed device, based on a twisted bilayer graphene (tBLG) on hexagonal boron nitride(hBN) shows immense promise as a scalable cryogenic memory. This device exhibits two topologically-protected variation tolerant non-volatile resistive states governed by the quantum anomalous Hall effect (QAHE). The implied memory states are read by the direction of the Hall voltage appearing across the two terminals of the device. The four terminal structure of the device and the Hall voltage property can be utilized to design a compact memory array suitable for in-memory computing. In this work, we design a simple in-memory binary multiplier, otherwise a complex circuit with traditional technologies, by utilizing the series addition of Hall voltages in the memory array. In addition, our novel in-memory binary-multiplier does not explicitly change the memory array architecture unlike DRAM in-memory multipliers. We also demonstrate bit-wise AND operation and partial product summation using our proposed design. Compared to a cutting-edge in-memory DRAM implementation our design is highly compact and significantly reduces processing complexity. Our simulations show an ultra-low power budget of 52nW /bit multiplication. Our designs demonstrate that QAHE devices are powerful candidates for future cryogenic in-memory computing