graph convolutional network (GCN) is a type of neural network that inference the new nodes based on the connectivity of the graphs. GCN requires high-calculation volume for processing, similar to other neural networks requiring significant calculation. In this paper, we propose a new hardware architecture for GCN that tackles the problem of wasted cycles during processing. We propose a new scheduler module that reduces memory access through aggregation and an optimized systolic array with improved delay. We compare our study with the state-of-the-art GCN accelerator and show outperforming results.