Both in academia and industry, a series of design methodologies based on evolutionary algorithms or machine learning techniques have been proposed to solve the problem of analog device sizing. However, these methods typically need a large number of circuit simulations during the optimization process and these simulations significantly increase the learning and computational costs. To tackle this problem, in this work, we propose DC-Model, a DC simulation-based neural network model that can greatly reduces the whole simulation time while been applied in the field of analog circuit optimization. DC-Model is inspired by the relationship between MOSFET dc operating point output parameters and circuit performances.