Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands

Simon Friedrich1, Shambhavi Balamuthu Sampath2, Robert Wittig1, Manoj Rohit Vemparala3, Nael Fasfous3, Emil Matus4, Walter Stechele5, Gerhard Fettweis1
1TU Dresden, 2BMW, 3BMW AG, 4Technische Universit├Ąt Dresden, 5TUM


Abstract

Modern deep neural networks specialized for object detection and semantic segmentation require specific operations to increase or preserve the resolution of their feature maps. Hence, more generic convolution layers called transposed and dilated convolutions are employed, adding a large number of zeros between the elements of the input features or weights. Usually, standard neural network hardware accelerators process these convolutions in a straightforward manner, without paying attention to the added zeros, resulting in an increased computation time. To cope with this problem, recent works propose to skip the redundant elements with additional hardware or solve the problem efficiently only for a limited range of dilation rates. We present a general approach for accelerating transposed and dilated convolutions that does not introduce any hardware overhead while supporting all dilation rates. To achieve this, we introduce a novel precision-scalable lightweight instruction set and memory scheme that can be applied to the different convolution variants. This results in a speed-up of 5.0 times in DeepLabV3+ outperforming the recently proposed design methods. The support of precision-scalable execution of all workloads further increases the speed-up in computation time shown for the PointPillars, DeepLabV3+, and ENet networks. Compared to the state-of-the-art commercial EdgeTPU, the instruction footprint of ResNet-50 of our designed accelerator is reduced by 77 percent.