Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit

Ashvinikumar Dongre and Gaurav Trivedi
Indian Institute of Technology Guwahati India


Resistive Random Access Memory (RRAM) is extensively used for the implementation of synapses. Even though a fresh metal oxide RRAM sampled in the pristine state cannot exhibit resistive switching before electroforming, the integration of the electroforming circuit in RRAM based applications has not been discussed thoroughly. A major challenge in integrating forming circuits is the high voltage required for the forming process. The 4T-1R structure used for the implementation extends the applicability of the array to inference as well as training. The ADCs used to convert the RRAM current to digital output consume lots of area and power. They also suffer from nonlinearity that needs special attention, increasing the design complexity. In this work, we present an RRAM array with a circuit designed to isolate the peripheral circuitry during forming to avoid malfunctioning. We also propose an RRAM current sensor circuit that converts the RRAM current to output pulses that are converted to digital output. Since there is a large gap between the two resistive states, the synapse is tolerant to 25% cycle-to-cycle and device-to-device variation. We test the functionality of the array in the presence of Random Transfer Noise (RTN) that is inherent to RRAM. The compliance current for the proposed design is 100 µA. The proposed RRAM array is 2.7× more energy efficient than the recent state-of-the-art designs. The area of the RRAM current sensor circuit is 18.1µm × 27.3µm.