Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA

Harshita Gupta1, Mayank Kabra2, Nitin Patwari3, Prashanth H C4, Madhav Rao5
1Thapar institute of information technology, Patiala, 2Student, 3Student, IIITB, 4IIIT-Bangalore, 5International Institute of Information Technology-Bangalore


The paper presents optimized implementations of Edwards curve digital signature algorithm~(EdDSA) which is based on a popular Ed25519 instance. When compared to current digital signature methods, this algorithm considerably reduces the execution time without compromising security. Despite being used in several popular applications, hardware implementation and characteristics is not reported. The proposed work aims to characterize on-chip EdDSA using four different state-of-the-art~(SOTA) multipliers. Multiplier forms critical design component in the EdDSA implementation, hence different SOTA multipliers are characterized for hardware metrics and its impact on the overall EdDSA module is investigated. Four different multipliers in the form of Conventional polynomial~(CA), Karatsuba~(KA), overlap-free-Karatsuba~(OKA), overlap-free based multilpier strategy~(OBS), along with the default array multiplier which are traditionally employed in hardware designs were investigated for 32-bit and 64-bit data format individually. These multipliers were further employed for designing on-chip EdDSA and its characteristics are presented. CA based on-chip EdDSA was characterized to work reliably at a maximum operating frequency of 120 MHz, whereas OBS and OKA derived on-chip EdDSA presented the most compact on-chip designs. The on-chip EdDSA work is a step towards attaining reliable on-chip cryptosystems in the future.