Nowadays, analog-mixed-signal (AMS) circuits are at the core of a large variety of devices targeting automotive, medical, communication, and energy applications. Despite their ubiquity, AMS design methodologies are not automated, rely on long manual iterations, and leverage slow SPICE-level simulation as golden standard. Moreover, SPICE simulations cannot help in verifying timing checks on the digital elements of the circuit, thus allowing possible escaped bugs in the final device. In this scenario, virtual prototypes are used to abstract the modeling of the AMS circuit to boost simulation speed, favor design reuse, and allow early evaluation of the design choices at the cost of a reduced accuracy.
This paper presents a novel virtual prototyping methodology for AMS circuits. Starting from the netlist of an AMS circuit and the description of the target technology library, the methodology automatically generates the SystemC models for the digital elements, extended with additional timing checks. To deliver the final timing-accurate AMS simulation, the generated SystemC models are then integrated into a co-simulation framework where the analog parts of the circuit are still simulated using SPICE. Experimental results demonstrated the validity of the proposed solution to deliver timing-accurate AMS simulations. The methodology can identify and check five timing violation classes for the digital parts of the circuit that are unchecked at SPICE level.