Approximate computing is accepted in error-tolerant applications including image and signal processing, where execution time is more critical than accuracy. Multipliers are the most common blocks that fall in the critical path limiting the performance and throughput of the system. Introduction of approximation in the multiplier units is considered highly beneficial due to reduced hardware requirements, provided the results are acceptable. In this work, approximate compressors are specifically designed for Radix-4 modified booth multiplier using the probabilistic approach to achieve power and footprint savings, with the performance benefits. Five variants of inexact multiplier designs were derived based on the placement of approximate compressors along the columns of the partial product matrix. The proposed designs were ASIC synthesized and characterized for hardware parameters and error metrics. A maximum improvement of 19.16%, 41.46%, and 51.53% are observed among the approximate multiplier variants compared to the exact version in terms of area, power-delay product (PDP), and area-power-delay product (APDP), respectively. All the proposed multipliers were evaluated for the applications: μ−law algorithm which is a standard companding algorithm primarily used in telecommunication systems, and image segmentation using k-means clustering which is an unsupervised learning algorithm popularly used in computer vision systems.