Abstract—Reconfigurable devices are gaining increasing attention as a feasible complement to prevailing CMOS technology. This paper focuses on enhancing the efficiency of Field-Programmable Gate Arrays (FPGAs) through the utilization of reconfigurable field-effective transistors (RFETs). Leveraging the multi-gate properties of RFETs, we design crucial FPGA elements, including SRAM-controlled multiplexer (MUX) and look-up tables (LUTs), to substantially improve the delay and energy consumption for the overall FPGA system. Furthermore, a framework is developed to thoroughly investigate the design space, including various device-level and system-level parameters. Benchmark tests demonstrate that optimal design configurations yield remarkable reductions of up to 70% in delay and 50% in energy-delay product (EDP) when compared to conventional CMOS counterparts.