This paper presents an energy-efficient time domain-based compute in-memory architecture to accelerate the deep neural networks (DNNs). This work focuses on improving the energy efficiency of the multiplication and accumulation (MAC) operation by performing it within the memory cell itself. The proposed approach utilizes time domain computing, which involves introducing a specific delay to a reference signal to perform MAC operations. To convert the time domain signal into a digital form, a time-to-digital converter (TDC) is employed. A 12T time domain-based bit cell generates the necessary delay, while a flash type TDC is used for time to digital conversion. The designed architecture has been implemented using a 45 nm CMOS technology, resulting in the development of a 128×64 SRAM CIM macro. Simulation results demonstrate that the proposed architecture achieved an energy efficiency of 941 TOPS/W at a frequency of 0.5 MHz and 1 V, which is 1.75× higher than the state-of-the-art. Furthermore, the system attained an inference accuracy of 96.7% and 84.52% when tested on the MNIST and CIFAR-10 dataset respectively.