Hyperdimensional Computing (HDC) is a brain-inspired classification paradigm that uses simple bitwise operations on high-dimensional vectors, making it attractive for edge AI accelerators. However, the scalability limits of FPGA-based HDC, in particular whether performance is constrained by logic resources or by routing, are not well understood. This work presents RouteHD, a class-parallel HDC accelerator on a Xilinx Alveo U200 FPGA, and uses it to empirically study routing-limited scalability at 10{,}000-bit dimensionality. We implement 8-way, 12-way, 16-way, and 26-way class-parallel designs and show that a 16-way configuration using 32.6\% of LUTs closes timing and achieves 0.179~M classifications/s, while a 26-way variant with similar LUT usage fails timing due to routing congestion. We further introduce a simple routing-pressure model that links HDC hypervector dimensionality, class count, and BRAM banking to the expected routing demand. The study shows that cyclic array partitioning with factors between 8 and 16 keeps the routing pressure below the congestion threshold, whereas fully partitioning all 26 classes creates 8{,}320 memory banks and overwhelms the routing fabric. These results identify routing congestion, not logic or BRAM capacity, as the dominant scalability bottleneck for class-parallel HDC on modern FPGAs and provide concrete guidelines for routing-aware HDC accelerator design.