In this paper, we propose a concurrent placement framework for face-to-face 3D-ICs that enables instance flipping during global placement. Modern 3D-ICs increasingly adopt heterogeneous dies built with different technology nodes to balance performance, cost, and functionality. This heterogeneity creates challenges for global placement due to varying cell sizes, pin offsets, and density characteristics across dies. To address this, we treat each die as an independent placement region, while inter-die connections are abstracted as IO constraints for simplified integration in the concurrent placement flow. Furthermore, we introduce the Flipping Weighted Average Wirelength (FWA-WL) model, which extends the classical Weighted-Average Wirelength model by incorporating flipping behavior throughout the placement process. This improves placement flexibility and helps reduce interconnect cost, particularly in mixed-size designs containing macros. Our approach is evaluated on the ICCAD 2023 Problem B benchmark suite with mixed-size designs containing macros. Experimental results show that our method achieves an average 3% HPWL reduction compared to a baseline without flipping. When combined with multi-die concurrent placement, the flipping mechanism leads to an overall 5% HPWL improvement, demonstrating the effectiveness of our framework in handling heterogeneous 3D-IC placement.