Multi-Node Timing and Power Estimation with Adapter-Based Transfer Learning

Luis Humberto Pena Trevino1, Eric Guerra Ribeiro2, Lirida Naviner1, Fady Abouzeid2, Philippe Roche2
1Télécom Paris, 2STMicroelectronics


Abstract

In recent years, Graph Neural Networks (GNNs) have shown promise in predicting post-route timing and power metrics early in the physical design process. However, a major challenge lies in their limited adaptability to different technology nodes. The training datasets for these models are highly dependent on specific technology nodes, corner parameters, and process variations, limiting their generalizability across various use cases. This constraint reduces their effectiveness in real-world applications, where performance analysis is required across different technology nodes, as in heterogeneous 3D integrated circuits.

To address these challenges, we propose a framework based on Graph Neural Networks enhanced with Parameter-Efficient Fine-Tuning (PEFT) techniques. This approach enables rapid and accurate estimation of power and timing metrics across different technology nodes or corners without requiring full retraining of a large pre-trained model.

Experimental results on open-source benchmark designs spanning three technology nodes demonstrate that our framework achieves up to two orders of magnitude runtime improvement, reduces error compared to commercial tools, and streamlines model training adaptability without compromising prediction accuracy.