With the rapid advancement of artificial intelligence (AI) technologies and the increasing proliferation of electronic devices, the demand for high-performance and secure printed circuit boards (PCBs) has grown substantially. In particular, the requirements for high-frequency operation, high-speed signal integrity, and enhanced security have become increasingly critical in modern PCB design. This study presents an integrated framework that incorporates test point insertion directly into the PCB routing process, simultaneously addressing testability and security concerns at the design stage. For the routing task, we propose a method that prioritizes nets by assigning routing sequences prior to trace generation. The A* search algorithm is then employed to perform multilayer routing, utilizing a customized heuristic function to minimize overall trace length while considering the known number of board layers. To determine optimal test point placement, we adopt a reinforcement learning approach, wherein an agent learns to select appropriate insertion actions guided by a carefully designed reward function. Experimental results demonstrate that the proposed approach achieves 100% routing success and full test point coverage across all evaluated PCB designs. The resulting design allows for improved accessibility for electrical testing and lays the groundwork for subsequent security assessment.