Test engineers developing validation programs for Analog-to-Digital Converters (ADCs) often lack early access to detailed circuit models or silicon, requiring reliable behavioral models that reflect specification-level error metrics. Existing approaches frequently approximate non-idealities such as Integral Non-Linearity (INL), offset, and gain in a statistical manner, leading to inaccuracies which undermine test development. This work introduces an algorithm for the creation of behavioral ADC models that enables precise, specification-driven control of static ADC errors - particularly enforcing a defined maximum INL - while preserving configured offset and gain values. Unlike statistical approaches, the algorithm deterministically generates compliant profiles and supports consistent instantiation across different bit resolutions. Simulations show accuracy and fast runtime via a one-time precomputation strategy, making the approach suitable for early-stage test development, virtual validation of test programs, and potentially large-scale SoC simulations.