This work evaluates the on-chip variability of the Anderson PUF by instantiating 128 designs on a Nexys A7 FPGA and collecting 100 UART samples per configuration using a lightweight host script. We vary MUX distance (MDIST) and flip-flop placement to study placement sensitivity, uniformity, and uniqueness. The FPGA results show no consistent relationship between chain length and bias; MDIST = 2 yields the most balanced outputs, while larger distances produce strong skew. Majority voting generates stable 128-bit responses for analysis. Findings highlight how routing and placement significantly influence PUF behavior in practice, thereby guiding more reliable FPGA-based implementations.