Reverse engineering of Look-Up table (LUT) level FPGA designs to high-level RTL helps in comprehension and verification of legacy designs. We propose a tool flow that extracts the operations performed by DSP primitives in FPGAs. DSP primitives can be used as standalone or chained structures in static or dynamic configurations. The proposed tool uses structural extraction and control signal analysis methods to reverse engineer and generate high-level RTL. DSP slices in FPGAs are commonly used to perform multiplication, multiply and accumulate, barrel shift, bit slice logic, and a few other operations. The developed technique can be used in tandem with existing tools to cover other FPGA elements such as carry elements and word-level modules. The proposed methodology is validated using real-world designs incorporating DSP primitives in complex configurations. The proposed tool extracts 100% of the operators and variables mapped to DSP slices in standalone or chained structures.