Modular multiplication is a critical operation in modern cryptographic systems, digital signatures, and secure data communication, where speed, power efficiency, and silicon utilization are equally important. Conventional architectures are typically optimized for a fixed operand width, resulting in redundant hardware and limited flexibility across various cryptographic protocols. To overcome this limitation, this paper presents a Reconfigurable Barrett Modular Multiplier (R-BMM) that unifies multiple operand configurations within a single scalable architecture. The proposed R-BMM dynamically supports three operational modes - one 256-bit, three 128-bit, or nine64-bit modular multiplications in parallel by reusing a single Karatsuba-based multiplier core. This reuse-driven approach eliminates the need for multiple dedicated multipliers, thereby achieving a significant reduction in hardware cost and switching activity while maintaining high computational throughput. The design incorporates optimized evaluation–interpolation (E,I) matrix transformations and a reconfigurable control mechanism that adapts the recombination logic based on the operand bit-width. The proposed architecture is implemented and evaluated on both FPGA and ASIC platforms to validate its scalability and portability. Experimental results demonstrate consistent performance gains across both implementations, including upto 52.17% area, 57.33% power, and 49.14% latency reductions compared to state-of-the-art designs. The proposed R-BMM thus establishes a unified and resource-efficient hardware framework capable of supporting a wide range of cryptographic applications with minimal overhead, offering a practical pathway toward high-performance, reconfigurable cryptographic accelerators.