High-precision and fault-tolerant multipliers are indispensable in energy-constrained computing platforms that operate under transient and process-induced errors. Conventional Triple Modular Redundancy (TMR) ensures strong reliability but suffers from high area and power overheads. The High-Precision Redundancy Multiplier (HPR-Mul) mitigates these costs through selective redundancy however, its tunable parameter introduces synthesis irregularities and inconsistent fault resilience. This work presents the Booth-Modified High-Precision Redundancy Multiplier (BM-HPR), which integrates Radix-4 Booth encoding into both full-precision (FP) and reduced-precision (RP) paths while eliminating the tunable parameter to achieve a fixed, synthesis-friendly datapath. The proposed design preserves the compact area of HPR while achieving up to 27.7% area reduction, 65.1% lower power consumption, and 31.8% faster delay compared to TMR. Additionally, it improves delay and power by 19.1% and 53.7%, respectively, over HPR. Fault-injection using random bit-flip models confirms bounded error rates suitable for error-resilient applications. When deployed in a ยต-law companding audio system, BM-HPR maintains a stable signal-tonoise ratio (SNR) and low error variance under injected faults, demonstrating its practical applicability. Implemented using the OpenROAD 45 nm flow, BM-HPR demonstrates a reproducible, energy-efficient, and fault-tolerant multiplier architecture suitable for embedded and real-time signal-processing workloads. All design files are made publicly available for reproducibility.