This paper presents POSEIDON, a novel RISC-V out-of-order processor optimized for posit arithmetic with inte- grated transformer acceleration targeting resource-constrained edge devices. The architecture introduces an innovative indirec- tion mechanism that enables efficient mixed-precision computa- tion by storing 32-bit integers in a separate Integer Data Store while maintaining compact posit-based data paths in the reorder buffer and issue queues. The processor integrates a systolic array-based accelerator subsystem with specialized processing element arrays for transformer operations including LayerNorm, Softmax, and GeLU. Experimental results demonstrate that POSEIDON achieves 90.0-93.5% accuracy on SST-2 sentiment analysis using 6-8-bit posits while reducing area by 58% and power consumption by 64% compared to conventional 32- bit floating-point implementations. The design maintains full programmability while providing 8.2× end-to-end speedup on transformer workloads through the integrated accelerator.