Aging-based covert-channel attacks on volatile memory have recently been demonstrated to compromise secret keys, secure images, and credential information on microcontrollers and SoCs manufactured by leading semiconductor vendors. Existing mitigation techniques either incur significant latency penalties or substantially increase area and power overhead. This paper proposes a novel architectural approach that leverages existing memory ECC scrubber hardware to periodically flip memory contents, preventing aging-based imprinting of stored data. To our knowledge, this work represents the first use of ECC infrastructure for bit flipping. We evaluate the proposed technique using industrial memory configurations with 56-bit ECC for each 256-bit data block, demonstrating marginal area and power increases of 0.98% and 2.11%, respectively, compared to traditional ECC scrubbing (baseline) for 1MB and 2MB memory modules. This overhead stems from additional logic in the SRAM memory controllers, while memory arrays remain unchanged. Compared to other systemlevel solutions, our technique achieves lower area and power penalties, along with significantly reduced performance overhead, as dead cycles during full memory flipping are reduced by up to 50% relative to state-of-the-art solutions.