Recently, aging-based covert channel attacks on volatile memories have been observed to compromise the secret keys, secure images, or credential information from several microcontrollers or SoCs manufactured by many prominent semiconductor IC vendors. The mitigation techniques either incur longer latency or increases the area and power overhead of SoCs significantly. This paper proposes a novel architectural approach of leveraging existing memory ECC scrubber hardware to periodically flip the memory content to prevent aging-based imprinting of stored contents. To our knowledge, for the first time, the ECC infrastructure is leveraged for bit flipping in this work. We evaluate the proposed technique on our multiple industrial memory configurations with 56-bit ECC for each 256-bit data, and show our method increases area and power marginally by 0.98% and 2.11%, respectively, compared with a traditional ECC scrubbing technique (i.e., baseline) for 1MB and 2MB memory modules. This overhead is due to the addition of logic in the SRAM memory controllers, as memory arrays are kept unchanged. Additionally, our technique shows lower area and power penalty than other system-level solutions, along with significantly lower performance penalty, as dead cycles during flipping the entire memory are reduced up to 50% compared to state-of-the-art system-level solutions.