Hyperdimensional Computing (HDC) is a brain-inspired learning paradigm that encodes information in high-dimensional vectors, enabling lightweight and efficient classification. While such representations improve accuracy and robustness, they also demand high computational, storage, and energy costs. To overcome these challenges, we propose a hardware-optimized RISC-V co-processor architecture for efficient HDC execution in low-power, resource-constrained systems. The co-processor leverages a custom instruction designed explicitly for HDC and integrates it using a Single Instruction, Multiple Data(SIMD) approach to enable parallelism and improve throughput.Furthermore, we present a software optimization scheme in the form of a genetic algorithm-based pruning framework that efficiently reduces the feature dimensionality, significantly lowering the computational burden on the co-processor with negligible accuracy loss. FPGA implementation results indicate notable gains, delivering a 16.44× improvement in energy efficiency and a 21.57× boost in throughput compared to the RISC-V cores, while achieving 9% savings in resource utilization and up to 24.78% reduction in power consumption relative to existing state-of-the-art (SOTA) designs. Additionally, our approach achieves a 65% reduction in the total number of clock cycles relative to SOTA designs. ASIC validation further confirms the benefits, showing upto 15.89% savings in silicon footprint, a 12.33% reduction in power consumption, while maintaining a comparable criticalpath delay relative to the baseline architecture.