Rapid Single-Flux Quantum (RSFQ) logic is a cutting-edge technology in superconducting electronics which greatly surpasses conventional CMOS logic in speed and power efficiency. Since RSFQ logic gates operate using Single Flux Quantum (SFQ) pulses, additional delay registers are required to balance data paths length and ensure proper data propagation. Previous works have shown that delay registers may account for up to half of the total gate count of a RSFQ circuit in practice, so it is important to minimize the number of delay registers used. In this paper, we propose some effective techniques to minimize the total number of delay registers during the post-mapping phase. Experimental results show that, compared to the state-of-the-art work based on minimum-area retiming, our approach achieved an 11.58\% improvement in delay register reduction in ISCAS benchmark sets and 5.37\% in IWLS and EPFL benchmark sets, with comparable runtime.