This paper introduces a novel design automation approach for securing Systems-on-Chip (SoCs) by natively integrating security as a primary optimization objective. Unlike existing design automation solutions that typically explore implementations for specific vulnerabilities, our method utilizes a purpose-built security metric specifically tailored for SoCs. Our optimization algorithm accepts a system specification (either as an application or an abstract SoC description) and generates a secured SoC architecture. This architecture enhances the regular SoC with an optimized security component. Optimization goals include critical metrics such as security, area, power, and latency, which are quantified as system risk. As a proof of concept, the proposed DSE of security tested three distinct security optimization strategies on a single system architecture: unrestricted resource and power utilization, restricted resource utilization, and restricted power utilization. The optimizer effectively returns all valid solutions that adhere to the user's defined risk constraints, clearly showcasing the inherent trade-offs between optimized system risk, Look-Up Table (LUT) utilization, and power consumption. The results demonstrate how designers can leverage this tool to identify optimal security and anomaly detection solutions tailored to their specific system architectures. For instance, while the most secure solution might demand thousands of LUTs, our tool facilitates balanced decision-making by considering security alongside resource, power, and latency constraints. This allows designers to incorporate security directly into the design process.