Standard cell libraries are foundational to digital IC design, yet their characterization—especially RTL-level behavioral modeling—remains highly time-consuming and labor-intensive. Existing approaches largely rely on manual RTL Verilog creation or commercial tools with limited automation, which hinders their adaptability and scalability. To tackle these challenges, we propose AutoBeaVer, an agentic workflow driven by large language models (LLMs) for automated behavioral modeling and verification. AutoBeaVer consists of two coordinated agents: a Testbench Agent and a Verilog Modeling Agent. The Testbench Agent parses transistor-level netlist descriptions and generates SPICE-level stimuli, serving as a golden reference. The Verilog Modeling Agent iteratively synthesizes RTL code and associated testbenches, leveraging LLM-based reasoning for self-correction and simulation-based validation. This ensures functional alignment between the generated RTL and the original transistor-level design. We evaluate AutoBeaVer on a comprehensive benchmark set comprising 105 digital standard cells, achieving a pass@1 of 97.14% and demonstrating substantially improved modeling accuracy and robustness over direct LLM-based generation. Our work significantly streamlines RTL behavioral modeling in library characterization, paving the way for broader automation in digital IC design.